ASIC IP RTL/TB Development – Looking for Freshers/Junior Engineers

Project Main Details

budget Project Budget
₹25,000.00
coins Average Bid
No bids placed yet.
location Location
category Category
category Skills
calendar Posted on
9th October 2020 7:04 PM
clock Time Left

30190042

proposals Proposals
0

Job Description :- 
 We are a group building high performance configurable ASIC IPs that can fit inside a variety of products ranging from low power IoT ASICs to good performance Desktop/Server ASICs.  The work centers around some of the advanced areas of chip design such as Cache Coherency, Virtual Channels and traffic performances, Pipelining for high-speed data and control logic, Clock-gating and Power-gating etc.   

The work is in an advanced prototype stage and we plan to launch a product down the line. The team has people with chip-design experience in MNCs over decade and background of colleges as Indian Institute of Technology.

Job Requirements :- 
1) We are looking for freshers or junior engineers who can code RTL and sub-unit Testbench from scratch with engineering supervision and broad level Microachitecture and  Architecture Specs.
2) The person needs to have an excellent/good Verilog/SystemVerilog/Perl Skillset.
The  coding will be Perl mixed Verilog/SV.
3) Knowledge of Make, Python, Bash is an advantage, but not mandatory.
4) The person needs to have a good understanding of the basic building blocks of an ASIC/FPGA design. Understanding of advanced concepts (as coherency) is an advantage, but not mandatory.
5) The person should have good energy to finish work in a timely manner, passion for RTL/TB coding, attention to details and humility to learn from right feedback.

Who can Apply :- 
1) Fresher/junior engineers looking for an opportunity.2) People looking for training/upscaling in the domain can apply. 3) People looking to explore in-depth from scratch ASIC design can also apply.
Benefits :- 

1) Opportunity to work in complex ASIC product design from scratch.
2) Opportunity to learn alongside experienced and passionate engineers.
3) Monthly Stipend/Remuneration. 
4) Facility to work remotely.

How To Apply :- 

Please mention below points –
1) Your expertise level in Perl / Verilog/ System Verilog.
2) Top 5 (only) basic building blocks whose microarchitecture/code you understand well and can be asked about – (say FIFOs, Tracker logic etc).
3) How lines you have coded yourself in Verilog/Perl/SystemVerilog till date. (If you are vast experienced, and have coded many a projects, plz mention that.)
4) Which area between design/verification you are more interested in.

Place holder budget/time. More can be discussed.

No proposals placed yet.
No images.
Job Description :-   We are a group building high performance configurable ASIC IPs that can fit inside a variety of products ranging from low power IoT ASICs to good performance Desktop/Server ASICs.  The work centers around some of the advanced areas of chip design such as Cache Coherency, Virtual Channels and tr
We are going to launch www.mimaas.in. We require domestic outbound call centers to sell our membership packages for our portalMinimum Agents Required: 50 Agents + 5 Team Leaders + 5 Document Collectors + 1 Manager Target: Minimum 30 Sales per month per agent Payout: 2 Lakhs per month per agent if they achieve the
Payment gateway integration in custom made e-commerce website (Payu money)